Stacked integrated circuits (ICs) have become a common package technique to increase processing and storage density of various electronic devices. Progress in miniaturizing various circuits and components has further allowed stacked integrated packages to become even more desired. However, miniaturizing has also created tradeoffs between size and function because the reduced size limits interconnect real estate. Thus, more processing chips or storage chips in the stack usually means significantly larger packages to accommodate additional interconnect real estate for the added chips. In addition, either significant processing such that each stacked chip is properly identified by the system or custom chips for each level of the stack may be necessary.